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General Description
ision
TM
Advanced Information Preliminary Datasheet
OV8610 Color CMOS SVGA (800 x 600) CAMERACHIPTM Applications
* * * * * Cellular phones Digital still cameras PC Multimedia PDAs Machine vision
The OV8610 CMOS image sensor is a single-chip video/imaging camera device designed to provide a high level of functionality in a single, small-footprint package. The device incorporates an 800 x 600 image array capable of operating at up to 15 frames per second (fps) in full resolution. Proprietary sensor technology utilizes advanced algorithms to cancel Fixed Pattern Noise (FPN), eliminate smearing, and drastically reduce blooming. All required camera functions including exposure control, gamma, gain, white balance, color matrix, color saturation, hue control, windowing, and more, are programmable through the serial SCCB interface. The device can be programmed to provide image output in different 8-bit or 16-bit digital formats.
Key Specifications
SVGA QSVGA Power Supply Power Active Requirements Standby Electronics Exposure Output Format Lens Size SVGA Max. Image Transfer Rate QSVGA Min. Illumination (3000K) S/N Ratio Dynamic Range Scan Mode Gamma Correction Pixel Size Dark Current Fixed Pattern Noise Image Area Package Dimensions Array Size 800 x 600 400 x 300 3.0 - 3.6 VDC < 30 mA (with 10 mA load) < 10 A Up to 648:1 (for selected fps) 10-bit digital raw RGB data 1/3" 15 fps 30 fps < 3 lux @ f1.2 > 48 dB (AGC off,Gamma=1) > 72 dB Progressive or Interlaced On/Off 0.45/1.0 6.2 m x 6.2 m < 0.2 nA/cm2 < 0.03% of VPEAK-TO-PEAK 4.96 mm x 3.72 mm .560 in. x .560 in.
Features
* * 480,000 pixels, 1/3" lens, SVGA/QSVGA format Data output formats include: - * * * * * * * ITU-601 - ITU-656 Choice of progressive scan/interlaced read Wide dynamic range, anti-blooming, zero smearing Electronic exposure/gain/white balance control Image quality controls - brightness, contrast, gamma, saturation, sharpness, windowing, hue, etc. Internal and external synchronization Line exposure option 3.3-Volt operation, low power dissipation - * * < 30 mA active power at 30 fps with 10 mA load - < 10 A in power-down mode Built in Gamma correction (0.45/1.00) SCCB programmable: - Color saturation, brightness, hue, white balance, exposure time, gain, etc.
Figure 1 OV8610 Pin Diagram
UV5/MIR UV0/ GAM MA UV1/ CC656 UV2/ QSVGA UV3/ ECLK0 UV4/ SLAEN UV7/B8 19 18 17 16 15 14 HREF/ VFLIP FODD/ SRAM VSYNC/ CSYS ADGND ADVDD VTO SCCBB VcCHG HVDD PWDN AVDD AGND 13 12 11 10 9 8 7 43 DEGND 44 DEVDD 45 SIO_1 46 SIO_0 47 RSVD 48 SGND 1 SVDD 2 RESET 3 AGCEN 4 FREX 5 VREQ 6 ASUB XCLK2 XCLK1 DGND DVDD UV6/ TVEN 20
30 DOGND DOVDD PCLK/ PWDB Y7 Y6 Y5/ SHARP Y4 31 32 33 34 35 36 37 38 39 40 41 42
29
28
27
26
25
24
23
22
21
Ordering Information
Product OV8610 (Color, SVGA, QSVGA, QQSVGA) Package CLCC-48
OV8610
Y3/RGB Y2/G2X Y1/PROG Y0/CBAR CHSYNC/ BW
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OV8610
Color CMOS SVGA (800 x 600) CAMERACHIPTM
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Functional Description
Figure 2 shows the functional block diagram of the OV8610 image sensor. The OV8610 includes: * Image Sensor Array (824 x 615 resolution) * Analog Signal Processor * Dual 10-Bit Analog-to-Digital Converters * Digital Data Formatter * Video Port * SCCB Interface
Figure 2 Functional Block Diagram
VTO
R G B
MUX
A/D Digital Data Formatter Video Port
Y[7:0]
Analog Signal Processor
Y Cb Cr
MUX
A/D
UV[7:0]
Column Sense Amp Row Select Exposure/Gain Detect Image Array (824 x 615) White Balance Detect
Control Registers
. . . .
Clock
Video Timing Generator Exposure/Gain Control White Balance Control SCCB Interface
XCLK1
XCLK2
HREF/ PCLK/ VSFRAM PWDB
VSYNC
FODD CHSYNC
MIR PROG AGCEN SIO_1 SIO_0 SCCBB
Image Sensor Array
The OV8610 sensor is a 1/3" CMOS imaging device. The sensor contains a total of 506,760 pixels (824 x 615). Its design is based on a field integration readout system with line-by-line transfer and an electronic rolling shutter with a synchronous pixel readout scheme. The color filter of the sensor consists of primary red, green, and blue filters arranged in the line-alternating Bayer pattern, RGRG/GBGB.
correction, automatic gain control (AGC), gamma correction, color balance, black level calibration, aperture correction, controls for picture luminance and chrominance, and hue control for color. The analog video signals are based on the following formula: Y = 0.59G + 0.31R + 0.11B U=R-Y V=B-Y where R, G, B are the equivalent color components in each pixel. YCbCr format is also supported, based on the following: Y = 0.59G + 0.31R + 0.11B Cr = 0.713 (R - Y) Cb = 0.564 (B - Y)
Analog Signal Processor
The image is captured by the 824 x 615 pixel image array and routed to the analog processing section where the majority of signal processing occurs. This block contains the circuitry that performs color separation, color 2 Proprietary to OmniVision Technologies
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Functional Description
Dual 10-Bit Analog-to-Digital Converters
The YCbCr or RGB data signal from the analog processing section is fed to two on-chip 10-bit analog-to-digital (A/D) converters: one for the Y/G channel and one shared by the CbCr/BR channels. The on-chip 10-bit A/D operates at up to 20 MHz, and is fully synchronous to the pixel rate. Actual conversion rate is related to the frame rate. A/D black-level calibration circuitry ensures: * Black level of Y/RGB is normalized to a value of 16 * Peak white level is limited to 240 * CbCr black level is 128 * CbCr Peak/bottom is 240/16 * RGB raw data output range is 16/240 NOTE: Values 0 and 255 are reserved for sync flag
Windowing
The windowing feature of the OV8610 image sensor allows user-definable window sizing as required by the application (see Figure 3). Window size setting (in pixels) ranges from 2 x 2 to 800 x 600, and can be positioned anywhere inside the 824 x 615 boundary. Note that modifying window size and/or position does not change frame or data rate. The OV8610 image sensor alters the assertion of the HREF signal to be consistent with the programmed horizontal and vertical region. The default output window is 800 x 600.
Figure 3 Windowing
Column Start HREF
R Column o w
Column End
Digital Data Formatter
The converted data stream is further conditioned in the digital formatter. The processed signal is delivered to the digital video port through the video multiplexer which routes the user-selected 8-, or 10-bit video data to the correct output pins.
Row Start HREF
Display Window
Row End Sensor Array Boundary
Image Processing
The algorithm used for the electronic exposure control is based on the brightness of the full image. The exposure is optimized for a "normal" scene that assumes the subject is well lit relative to the background. In situations where the image is not well lit, the automatic exposure control (AEC) white/black ratio may be adjusted to suit the needs of the application.
Zoom Video (ZV)
The OV8610 image sensor includes a Zoom Video (ZV) function that supports standard ZV port interface timing. Signals available include VSYNC, CHSYNC, PCLK and 16-bit data bus: Y[7:0] and UV[7:0]. The rising edge of PCLK clocks data into the ZV port (see Figure 6).
Additional on-chip functions include:
* * AGC that provides a gain boost of up to 24 dB White balance control that enables setting of proper color temperature and can be programmed for automatic or manual operation. Separate saturation, brightness, hue, and sharpness adjustments allow for further fine-tuning of the picture quality and characteristics.
QSVGA-Skip
A QSVGA mode is available for applications where higher resolution image capture is not required. Only half of the pixel rate is required when programmed in same frame rate with sub-sampling method. If retaining the same pixel rate with the skip method, the maximum frame rate is 120. Default resolution is 400 x 300 pixels and can be programmed for other resolutions. Refer to Table 6 and Table 7 for further information.
*
The OV8610 image sensor also provides control over the White Balance ratio for increasing/decreasing the image field Red/Blue component ratio. The sensor provides a default setting that may be sufficient for many applications.
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OV8610
QQSVGA-Skip
Color CMOS SVGA (800 x 600) CAMERACHIPTM
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8-bit data mode
In this mode, video information is output in Cb Y Cr Y order using the Y port only and running at twice the pixel rate during which the UV port is inactive (see Table 2). The OV8610 image sensor provides VSYNC, HREF, PCLK, FODD, and CHSYNC as standard video timing signals. In ITU-656 modes, the OV8610 image sensor asserts Start of Active Video (SAV) and End of Active Video (EAV) to indicate the beginning and ending of the HREF window. As a result, SAV and EAV change with the active pixel window. The OV8610 image sensor offers flexibility in YUV output format. The device may be programmed to standard YUV 4:2:2. The device may also be configured to "swap" the UV sequence. When swapped, the UV channel output sequence in the 16-bit configuration becomes: V U V U*** The 8-bit configuration becomes: V Y U Y***. The third format available in the 8-bit configuration is the Y/UV sequence swap: Y U Y V***.
A QQSVGA mode is available for further resolution decrease. Two methods are used to get this mode, sub-sampling and skip. Sub-sampling can get better quality than skip but skip can attain a higher frame rate. The maximum frame rate is 240 for QQSVGA and the default resolution is 200 x 150.
Video Port
The video output port of the OV8610 image sensor provides a number of output format/standard options to suit many different application requirements. Table 1 indicates the output formats available. These formats are user-programmable through the SCCB interface.
YUV Output
The OV8610 supports ITU-656 and ITU-601 output formats, providing VSYNC, HREF, and PCLK as standard output video timing signals.
ITU-601/ITU-656
The OV8610 image sensor supports both ITU-601 and ITU-656 output formats in the following configurations (see Table 3 and Figure 4 for further details):
16-bit, 4:2:2 Format
This mode complies with the 60/50 Hz ITU-601 timing standard (see Table 3).
RGB Raw Data Output
The OV8610 image sensor can also be programmed to provide 8-bit RGB raw data output. The output sequence is matched to the OV8610 color filter pattern. The video output appears in Y channel only and the UV channel is disabled in 8-bit RGB raw data. The output sequence is B G R G.
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Functional Description
Table 1
Digital Output Formats
Resolution 16-bit Pixel Clock 800 x 600 Y
a
400 x 300 Y Y Y Y Y Y
200 x 150 Y Y Y Y Y Y
YUV
8-bit ITU-656 16-bit
Y Y Y Y Y
RGB
8-bit ITU-656b
Y/UV Swapc
16-bit 8-bit YUVd RGBe 16-bit 8-bit 16-bit 8-bit Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
U/V Swap
YG
Single-Line RGB Raw Data MSB/LSB Swap
a. b. c. d. e.
"Y" indicates mode/combination is supported by the OV8610 Output is 8-bit in RGB ITU-656 format. SAV and EAV are inserted at the beginning and ending of HREF, which synchronizes the acquisition of VSYNC and HSYNC. 8-bit data bus configuration (without VSYNC and CHSYNC) can provide timing and data in this format. Y/UV swap is valid in 8-bit format only. Y channel output sequence is Y U Y V. U/V swap means UV channel output sequence swaps in YUV format (i.e., V U V U ... for 16-bit and V Y U Y ... for 8-bit). U/V swap means neighbor row B R output sequence swaps in RGB format. Refer to RGB Raw Data Output for further details.
Table 2
4:2:2 8-bit Format
Pixel Byte Sequence
U7 U6 U5 U4 U3 U2 U1 U0 0 01 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 V7 V6 V5 V4 V3 V2 V1 V0 1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U7 U6 U5 U4 U3 U2 U1 U0 2 23 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 V7 V6 V5 V4 V3 V2 V1 V0 3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
Data Bus
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y Frame UV Frame
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Table 3
Color CMOS SVGA (800 x 600) CAMERACHIPTM 4:2:2 16-bit Format
Data Bus Pixel Byte Sequence Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 0 01 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 2 23 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 4 45
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Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 Y Frame UV Frame
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 5
Table 4 shows the default Y/UV channel output port relationship before an MSB/LSB swap.
Table 4
Default Output Sequence
MSB LSB Y6 Y6 Y5 Y5 Y4 Y4 Y3 Y3 Y2 Y2 Y1 Y1 Y0 Y0
Output port Internal output data
Y7 Y7
Table 5 and Table 6 shows the relationship after an MSB/LSB swap changes.
Table 5
Swapped MSB/LSB Output Sequence
MSB LSB Y6 Y1 Y5 Y2 Y4 Y3 Y3 Y4 Y2 Y5 Y1 Y6 Y0 Y7
Output port Internal output data
Y7 Y0
Table 6
QSVGA Digital Output Format (YUV Beginning-of-Line)
Pixel No. 1 Y0 U0, V0 2 Y1 U1, V1 3 Y2 U2, V2 4 Y3 U3, V3 5 Y4 U4, V4 6 Y5 U5, V5 7 Y6 U6, V6 8 Y7 U7, V7
Y UV
Y channel output U2Y2V3 Y3U6 Y6V7 Y7 U10Y10 V11Y11... Every other pixel (total 400 pixels) and every other line (total 300 lines) is output in each frame. 6 Proprietary to OmniVision Technologies Version 2.3, April 8, 2003
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Functional Description
The pixel pattern for the RGB raw data format is shown in Table 7.
Table 7
R/C 1 2 3 4
RGB Raw Data Format
1 B1,1 G2,1 B3,1 G4,1 2 G1,2 R2,2 G3,2 R4,2 3 B1,3 G2,3 B3,3 G4,3 4 G1,4 R2,4 G3,4 R4,4 ... ... ... ... ... 821 B1,821 G2,821 B3,821 G4,821 822 G1,822 R2,822 G3,822 R4,822 823 B1,823 G2,823 B3,823 G4,823 824 G1,824 R2,824 G3,824 R4,824
613 614 615 *
B613,1 G614,1 B615,1
G613,2 R614,2 G615,2
B613,3 G614,3 B615,3
G613,4 R614,4 G615,4
... ... ...
B613,821 G614,821 B615,821
G613,822 R614,822 G615,822
B613,823 G614,823 B615,823
G613,824 R614,824 G615,824
RGB full resolution progressive scan mode (total 614 HREFs) - - - - First HREF Y channel output unstable data Second HREF Y channel output B11G21 R22 G12 B13G23 R24 G14 . . . Third HREF Y channel output B31 G21 R22 G32 B33 G23 R24 G34 . . . Every line of data is output twice for each frame
*
- PCLK is double RGB QSVGA resolution progressive scan mode (total 300 HREFs) - - - - First HREF Y channel output B11G21 R22 G12 B15G25 R26 G16 . . . Second HREF Y channel output B31G41 R42 G32 B35G45 R46 G36 . . . Third HREF Y channel output B51 G61 R62 G52 B55 G65 R66 G56 . . . Every line of data is output once for each frame
*
- Maximum frame rate is 60 fps RGB full resolution raw data one line format (total 600 HREFs) - - - First HREF Y channel output B11 G12 B13 G14 . . . Second HREF Y channel output G21 R22 G23 R24 . . . Third HREF Y channel output B31 G32 B33 G34 . . .
*
- PCLK rising edge latch data bus RGB QSVGA resolution raw data one line format (total 300 HREFs) - - - - - First HREF Y channel output B11 G12 B15 G16 . . . Second HREF Y channel output G21 R22 G25 R26 . . . Third HREF Y channel output B51 G52 B55 G56 . . . Third HREF Y channel output G61 R62 G65 R66 . . . PCLK rising edge latch data bus
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Frame Exposure Mode
OV8610 supports frame exposure mode. In this mode, FREX (pin 4 - see "FREX" on page 9) is asserted by an external master device to set exposure time. The pixel array is quickly pre-charged when FREX is set to "1". OV8610 captures the image during the time period when FREX remains high. The video data stream is delivered to the output port in a line-by-line manner after FREX switches to "0". It should be noted that FREX must remain high long enough to ensure the entire image array has been pre-charged. When data is being output from OV8610, care must be taken so as not to expose the image array to light. This may affect the integrity of the image data captured. A mechanical shutter synchronized with the frame exposure rate can be used to minimize this situation. The timing of frame exposure mode is shown in Figure 7.
Power-Down Mode
Two methods are available to place the OV8610 into power-down mode: hardware power-down and SCCB software power-down. To initiate hardware power-down, the PWDN pin (pin 9 see "PWDN" on page 9) must be tied to high (+3.3 VDC). When this occurs, the OV8610 internal device clock is halted and all internal counters are reset. The current draw is less than 10 A in this standby mode. Executing a software power-down through the SCCB interface suspends internal circuit activity, but does not halt the device clock. The current requirements drop to less than 1 mA in this mode.
SCCB Interface
The method to configure OV8610 is to use its on-chip SCCB register programming capability. The SCCB interface provides access to all of the device's programmable internal registers.
Reset
The OV8610 includes a RESET pin (pin 2 - see "RESET" on page 9) that forces a complete hardware reset when it is pulled high (VCC). The OV8610 clears all registers and resets to their default values when a hardware reset occurs. Reset can also be initiated through the SCCB interface.
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Pin Description
Pin Description
Table 8
Pin Number 01 02
Pin Description
Name SVDD RESET Pin Type VIN Function/Description Array power (+3.3 VDC) - bypass to ground using a 0.1 F capacitor
Function Chip reset, active high. Resets all control registers to factory defaults. (default = 0) Automatic Gain Control (AGC) Selection 0: Disable AGC 1: Enable AGC Note: This function is disabled when OV8610 sensor is configured in SCCB low mode. In SCCB low mode, this pin is an SCCB chip select.
03
AGCEN
Function (default = 0)
04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
FREX VREQ ASUB AGND AVDD PWDN HVDD VcCHG SCCBBa VTO ADVDD ADGND VSYNC/CSYS FODD/SRAM HREF/VFLIP UV7/B8b UV6/TVENb UV5/MIRb UV4/SLAENb UV3/ECLKOb
Function (default = 0)
Frame Exposure Control 0: Disables frame exposure control 1: Enables frame exposure control
VREF (1.5V) Array reference - connect to ground using a 0.1 F capacitor VIN VIN VIN Function (default = 0) Analog substrate voltage Analog ground Analog power supply (+3.3 VDC) - bypass to ground using a 0.1 F capacitor Power-down Mode Selection 0: Operating mode 1: Power down mode
VREF (1.5V) Charge pump out voltage. Doubler must be enabled. VREF (2.7V) Internal voltage reference - bypass to ground using a 0.1 F capacitor Function (default = 0) Output VIN VIN Output Output Output Output Output Output Output Output SCCB Enable Selection 0: 1: Selects internal register setting control and enables SCCB interface Enables I/O input pin power on latch setting control
CCIR analog composite signal output - for test purposes only Analog power supply (+3.3 VDC) - bypass to ground using a 0.1 F capacitor Analog signal ground Vertical sync output. At power-up, read as CSYS. Field ID FODD output. At power-up, read as SRAM. HREF output. At power-up, read as VFLIP. U video component output bit[7]. At power-up, sampled as B8. U video component output bit[6]. At power-up, sampled as TVEN. U video component output bit[5]. At power-up, sampled as MIR. U video component output bit[4]. At power-up, sampled as SLAEN. U video component output bit[3]. At power-up, sampled as ECLKO.
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Table 8
Pin Number 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
a. b.
Color CMOS SVGA (800 x 600) CAMERACHIPTM Pin Description (Continued)
Name UV2/QSVGAb UV1/CC656b UV0/GAMMA XCLK1 XCLK2 DVDD DGND DOGND DOVDD PCLK/PWDB Y7 Y6 Y5/SHARP Y4 Y3/RGB Y2/G2X Y1/PROG Y0/CBAR CHSYNC/RSVD DEGND DEVDD SIO_1 SIO_0 RSVD SGND
b
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Pin Type Output Output Output Input Output VIN VIN VIN VIN Output Output Output Output Output Output Output Output Output Output VIN VIN Input I/O - VIN
Function/Description U video component output bit[2]. At power-up, sampled as QSVGA. U video component output bit[1]. At power-up, sampled as CC656. U video component output bit[0]. At power-up, sampled as GAMMA. Crystal clock input Crystal clock output Digital power supply (+3.3 VDC) - bypass to ground using a 0.1 F capacitor Digital ground Digital interface output buffer ground Digital output buffer supply (+3.3 VDC) - bypass to ground using a 0.1 F capacitor PCLK output. At power-up, sampled as charge pump enable. Y video component output bit[7] Y video component output bit[6] Y video component output bit[5]. At power-up, sampled as SHARP. Y video component output bit[4] Y video component output bit[3]. At power-up, sampled as RGB. Y video component output bit[2]. At power-up, sampled as G2X. Y video component output bit[1]. At power-up, sampled as PROG. Y video component output bit[0]. At power-up, sampled as CBAR. CHSYNC output. Decoder ground Decoder power supply (+3.3 VDC) - bypass to ground using a 0.1 F capacitor SCCB serial interface clock input SCCB serial interface data I/O Reserved - DO NOT connect Array ground
All I/O latch input pins are effective only when pin 12 (SCCBB) is high. Otherwise, all pin functions are regulated by the register settings. Output is not available in one-port mode.
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Electrical Characteristics
Electrical Characteristics
Table 9 Operating Conditions
Parameter Operating temperature Storage temperature Operating humidity Storage humidity Min 0 -40 TBD TBD Max 40 125 TBD TBD Unit C C
Table 10
Symbol Supply VDD1
DC Characteristics (0C < TA < 85C, Voltages referenced to GND)
Parameter Min Typ Max Unit
Supply voltage (DEVDD, ADVDD, AVDD, DVDD, DOVDD) Supply current (at 30 fps and 3.3 V digital I/O plus 1 TTL loading on 16-bit data bus) Standby supply current
3.0
3.3
3.6
V
IDD1 IDD2
30 8
35 10
mA A
Digital Inputs VIL VIH CIN Input voltage LOW Input voltage HIGH Input capacitor 2 10 0.8 V V pF
Digital Outputs (standard loading 25 pF, 1.2 K to 3 V) VOH VOL SCCB Inputs VIL VIH VIL VIH SIO_0 and SIO_1 (DOVDD = 5V) SIO_0 and SIO_1 (DOVDD = 5V) SIO_0 and SIO_1 (DOVDD = 3V) SIO_0 and SIO_1 (DOVDD = 3V) -0.5 3.0 -0.5 2.5 3.3 0 3.3 1.5 VDD + 0.5 1 VDD + 0.5 V V V V Output voltage HIGH Output voltage LOW 2.4 0.6 V V
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Table 11
Symbol
AC Characteristics (TA = 25C, VDD = 3V)
Parameter Min Typ Max Unit
RGB/YCbCr Output ISO Maximum sourcing current DC level at zero signal VY YPP 100% amplitude (without sync) Sync amplitude ADC Parameters B DIFF DLE ILE DC differential linearity error DC integral linearity error 0.5 1 LSB LSB Analog bandwidth TBD MHz 15 1.2 1 0.4 mA V V V
Table 12
Symbol
Timing Characteristics
Parameter Min Typ Max Unit
Oscillator and Clock Input fOSC tr, tf Frequency (XCLK1 and XCLK2) Clock input rise/fall time Clock input duty cycle SCCB Timing (400 Kbps) (see Figure 8) fSIO_C tLOW tHIGH tAA tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tR, tF tDH Clock Frequency Clock Low Period Clock High Period SIO_C low to Data Out valid Bus free time before new START START condition Hold time START condition Setup time Data-in Hold time Data-in Setup time STOP condition Setup time SCCB Rise/Fall times Data-out Hold time 50 1.3 600 100 1.3 600 600 0 100 600 300 900 400 KHz s ns ns s ns ns s ns ns ns ns 45 50 10 20 40 5 55 MHz ns %
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Electrical Characteristics
Table 12
Symbol
Timing Characteristics (Continued)
Parameter Min Typ Max Unit
Digital Timing tPCLK tPCLK tr, tf tPDD tPHD PCLK cycle time (16-bit operation) PCLK cycle time (8-bit operation) PCLK rise/fall time PCLK to data valid PCLK to HREF delay 5 10 50 50 5 5 20 ns ns ns ns ns
Zoom Video Port AC Parameters (see Figure 6) t1 t2 t3 t4 t5 t6 t7 t8 PCLK fall time PCLK low time PCLK rise time PCLK high time PCLK period Y/UV/HREF setup time Y/UV/HREF hold time VSYNC setup/hold time to HREF 4 21 4 21 50 5 20 1 8 8 ns ns ns ns ns ns ns s
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Timing Specifications
Figure 4 Pixel Data Bus (YUV Output) Timing
TCLK PCLK TSU HREF THD
Y[7:0] UV[7:0]
10 80
Y U
Y V
10 80
Repeat for All Data Bytes
Pixel Data 16-bit Timing (PCLK rising edge latches data bus)
TCLK PCLK TSU HREF T HD
Y[7:0]
10
80
10
U
Y
V
Y
80
10
Repeat for All Data Bytes
Pixel Data 8-bit Timing (PCLK rising edge latches data bus)
NOTES: 1. 2. 3.
TCLK is the pixel clock period. T CLK = 50 ns for 16-bit output and T clock is 20 MHz with on-chip 2x PLL. TSU is the setup time for HREF with a maximum time of 15 ns. THD is the hold time for HREF with a maximum time of 15 ns.
CLK
= 25 ns for 8-bit output if the system
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Timing Specifications
Figure 5 Pixel Data Bus (RGB Output) Timing
T CLK PCLK T SU HREF THD
Y[7:0] UV[7:0]
10 10
G B
R G
10 10
Repeat for All Data Bytes
Pixel Data 16-bit Timing (PCLK rising edge latches data bus)
T CLK PCLK T SU HREF THD
Y[7:0]
10
10
10
B
G
R
G
10
10
Repeat for All Data Bytes
Pixel Data 8-bit Timing (PCLK rising edge latches data bus)
NOTES: 1. 2. 3.
TCLK is the pixel clock period. T CLK = 50 ns for 16-bit output and T clock is 20 MHz with on-chip 2x PLL. TSU is the setup time for HREF with a maximum time of 15 ns. THD is the hold time for HREF with a maximum time of 15 ns.
CLK
= 25 ns for 8-bit output if the system
Version 2.3, April 8, 2003
Proprietary to OmniVision Technologies
15
OV8610
Color CMOS SVGA (800 x 600) CAMERACHIPTM
Omni
ision
Figure 6 Zoom Video Port Timing
Even Field 1 (FODD=0) VSYNC t8 t8 Odd Field 1 (FODD=1)
HREF t6 t4 PCLK t1 t2 Y[7:0]/UV[7:0] t3 t5 t7
1
2 Valid Data Horizontal Timing
799
800
VSYNC T VS Y[7:0]/UV[7:0] 1 Line TVE
T LINE
Vertical Timing NOTE: Zoom Video Port format output signal includes: VSYNC: Vertical sync pulse HREF: Horizontal valid data output window PCLK: Pixel clock used to clock valid data and CHSYNC into Zoom Video Port. Default frequency is 20 MHz when using 20 MHz as system clock plus 2x PLL implemented on the chip. Rising edge of PCLK is used to clock 16-bit data. Y[7:0]: 8-bit luminance data bus UV[7:0]: 8-bit chrominance data bus
16
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Omni
ision
Timing Specifications
Figure 7 Frame Exposure Timing
FREX TIN HSYNC Precharge begins at the rising edge of HSYNC ARRAY PRECHARGE T PR Array Exposure Period T EX 1 Frame (612 Lines) Valid Data Black Data T HD Head of Valid Data (8 Lines) VSYNC Next Frame TSET Mechanical Shutter Off T HS
Array Precharge Period T PR DATA OUTPUT Invalid Data
HREF
NOTES:
1. T PR =612 x 4 x T CLK or T PR =858xT clk depends on mode selecton. T if the system clock is 27MHz . T
CLK
CLK
is internal pixel period. T
CLK
=74ns
will increase with the clock divider CLK[5:0]. < THS .
2. T EX is array exposure time which is decided by external master device. 3. T IN is uncertain time due to the using of HSYNC rising edge to synchronize FREX. T 4. There are 8 lines data output before valid data after FREX=0. T 5. T SET =T IN + T PR + T EX . T SET > T PR + T IN . The exposure time setting resolution is T uncertainty of T IN .
IN
=4 THS. Valid data is output when HREF=1. HD
HS
(one line) due to the
Figure 8 SCCB Timing Diagram
tF t LOW SIO_1 t SU:STA SIO_0 IN tAA t DH t HD:STA t HD:DAT t SU:DAT tSU:STO t HIGH tR
t BUF
SIO_0 OUT
SCCBB
Version 2.3, April 8, 2003
Proprietary to OmniVision Technologies
17
OV8610
Color CMOS SVGA (800 x 600) CAMERACHIPTM
Omni
ision
OV8610 Light Response
Figure 9 OV8610 Light Response
Normalized Spectrum Response
Monochrome Response
18
Proprietary to OmniVision Technologies
Version 2.3, April 8, 2003
Omni
ision
Register Set
Register Set
Table 13 provides a list and description of the Device Control registers contained in the OV8610. The device slave addresses for the OV8610 are A0 for write and A1 for read.
Table 13
Address (Hex)
Device Control Register List
Register Name Default (Hex) R/W AGC Gain Control Bit[7:6]: Bit[5:0]: Reserved Current gain setting Description
00
GAIN
00
RW
Note: This register is updated automatically if AGC is enabled. The internal controller stores the optimal gain value in this register. The current value is stored in this register if AGC is not enabled. Blue Gain Control 01 BLUE 80 RW Bit[7:0]: Blue channel gain balance value * Range: [00] to [FF]
Red Gain Control 02 RED 80 RW Bit[7:0]: Red channel gain balance value * Range: [00] to [FF]
Color Saturation Control 03 SAT 80 RW Bit[7:4]: Bit[3:0]: Saturation adjustment * Range: [00] to [F8] Reserved
Color Hue Control 04 HUE 10 RW Bit[7:6]: Bit[5]: Bit[4:0]: Reserved Brightness Control 06 07-09 0A 0B BRT RSVD PID VER 80 XX 86 B0 RW - R R Bit[7:0]: Reserved Product ID Number (Read only) Product Version Number (Read only) White Balance Background - Blue Channel 0C ABLU 20 RW Bit[7:6]: Bit[5:0]: Reserved White balance blue ratio adjustment * Range: [3F] is most blue Brightness adjustment * Range: [00] to [FF] Reserved Enable hue control Hue control * Range: -30 to 30
05
RSVD
XX
-
White Balance Background - Red Channel 0D ARED 20 RW Bit[7:6]: Bit[5:0]: Reserved White balance red ratio adjustment * Range: [3F] is most red Proprietary to OmniVision Technologies 19
Version 2.3, April 8, 2003
OV8610
Table 13
Address (Hex) 0E-0F
Color CMOS SVGA (800 x 600) CAMERACHIPTM Device Control Register List
Register Name RSVD Default (Hex) XX R/W - Reserved Automatic Exposure Control Description
Omni
ision
10
AEC
A2
RW
Bit[7:0]:
Set exposure time
TEX = 4 x TLINE x AEC[7:0] Clock Rate Control Bit[7:6]: Sync output polarity selection 00: HSYNC = Neg, CHSYNC = Neg, VSYNC = Pos 01: HSYNC = Neg, CHSYNC = Neg, VSYNC = Neg 10: HSYNC = Pos, CHSYNC = Neg, VSYNC = Pos 11: HSYNC = Pos, CHSYNC = Pos, VSYNC = Pos Clock pre-scalar
11
CLKRC
00
RW Bit[5:0]:
CLK = (MAIN_CLOCK / (CLKRC[5:0] + 1) x 2) / n where n = 1, if COMD[5] = 1 (see "COMD" on page 22) and n = 2 otherwise. Common Control A Bit[7]: SRST 1: Initiates soft reset. All register are set to factory default values after which the chip resumes normal operation MIRR 1: Selects mirror image AGC enable 1: Enables AGC Digital output format 0: U Y V Y U Y V Y (8-bit) 1: Y U Y V Y U Y V (8-bit) Select video data output 0: YCbCr 1: RGB Auto White Balance (AWB) 0: Disable AWB 1: Enable AWB Color bar test pattern 1: Enable color bar test pattern ADC BLC method 0: More stable but less precise 1: Precise
Bit[6]: Bit[5]: Bit[4]: 12 COMA 24 RW
Bit[3]:
Bit[2]:
Bit[1]: Bit[0]:
20
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Omni
ision
Register Set
Table 13
Address (Hex)
Device Control Register List
Register Name Default (Hex) R/W Common Control B Bit[7]: VSYNC output selection 0: VSYNC always output 1: No VSYNC output when no valid data AGC/AWB register SCCB update option 0: Updated after VSYNC 1: Updated immediately after SCCB input Select data format 0: Select 16-bit format 1: Select 8-bit format, YCbCr and RGB is multiplexed to 8-bit Y bus, UV bus is tri-stated Digital output 1: Enable digital output in ITU-656 format CHSYNC output 0: Horizontal sync 1: Composite sync Y and UV buses 0: Enable both buses 1: Tri-state Y and UV buses Frame transfer 1: Initiate single frame transfer Auto adjust mode enable 0: Disable auto adjust mode 1: Enable auto adjust mode Description
Bit[6]:
Bit[5]:
13
COMB
01
RW
Bit[4]: Bit[3]:
Bit[2]:
Bit[1]: Bit[0]:
Common Control C Bit[7]: AWB threshold selection 0: More accurate but less stable 1: More stable but less accurate UV option 0: Normal color mode 1: UV always zero QSVGA digital output format selection 0: 800 x 600 1: 400 x 300 Field/Frame vertical sync output in VSYNC port selection 0: Field vertical sync, effective in interlaced mode 1: Frame sync, only ODD field vertical sync HREF polarity selection 0: HREF positive 1: HREF negative Gamma selection 0: RGB gamma is 1 1: RGB gamma ON Reserved
Bit[6]:
Bit[5]: 14 COMC 00 RW
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1:0]:
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Proprietary to OmniVision Technologies
21
OV8610
Table 13
Address (Hex)
Color CMOS SVGA (800 x 600) CAMERACHIPTM Device Control Register List
Register Name Default (Hex) R/W Common Control D Bit[7]: Description
Omni
ision
Bit[6]:
ADC clock 50% duty cycle selection 0: Non-50% duty cycle 1: 50% duty cycle PCLK polarity selection 0: OV8610 output data at PCLK falling edge and data bus will be stable at PCLK rising edge 1: Rising edge output data and stable at PCLK falling edge Digital 2x PLL disable 0: Enable 1: Disable Array vertical second stage skip mode enable. Frame rate will double and only effective in progressive scan mode, while first stage sub-sampling is disabled. AGCEN pin option 0: Normal AGCEN pin 1: AGCEN as data output enable/disable pin control Reserved Enable NTSC timing - only part of full resolution output UV digital output sequence exchange control 0: V U V U (for 16-bit) and V Y U Y (for 8-bit) 1: UV UV (for 16-bit) and U Y V Y (for 8-bit)
Bit[5]: 15 COMD 01 RW
Bit[4]:
Bit[3]:
Bit[2]: Bit[1]: Bit[0]:
16
FSD
03
RW
Field Slot Division Bit[7:2]: Field interval selection It is functional in EVEN and ODD mode defined by FSD[1:0]. It is disabled in OFF and FRAME modes. The purpose of FSD[7:2] is to divide the video signal into programmed number of time slots and allow HREF to be active for only one field in every FSD[7:2] fields. It does not affect the video data or pixel rate. FSD[7:2] disables digital data output. There is only black reference level at the output. FSD[7:2] = 1 outputs every field. FSD[7:2] outputs one field and disables one field, etc. Bit[1:0]: Field mode selection Each frame consists of two fields, odd and even. FSD[1:0] defines the assertion of HREF in relation to the two fields. 00: OFF mode - HREF is not asserted in both fields, one exception is the single frame transfer operation (see "COMB" on page 21). 01: ODD mode - HREF is asserted in odd fields only 10: EVEN mode - HREF is asserted in even fields only 11: FRAME mode - HREF is asserted in both odd and even fields. FSD[7:2] is disabled.
22
Proprietary to OmniVision Technologies
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Omni
ision
Register Set
Table 13
Address (Hex)
Device Control Register List
Register Name Default (Hex) R/W Description Horizontal HREF Start Bit[7:0]: Selects the starting point of the HREF window. Each LSB represents four pixels in SVGA resolution mode, two pixels in QSVGA resolution mode, and one pixel for QCIF resolution mode. This value is set based on an internal column counter. The default value corresponds to a window size 800 pixels wide. Maximum window size is 824 pixels. * HREFST[7:0] should be less than HREFEND[7:0] (see "HREFEND" on page 23) Horizontal HREF End Bit[7:0]: Selects the ending point of the HREF window. Each LSB represents four pixels in full resolution, two pixels in QSVGA mode, and one pixel for QCIF resolution mode. This value is set based on an internal column counter. The default value corresponds to the last available pixel. * HREFEND[7:0] should be larger than HREFST[7:0] (see "HREFST" on page 23) Vertical Line Start Bit[7:0]: Selects the starting row of the vertical window. In full resolution mode, each LSB represents two scan lines in one field in interlaced scan mode and four scan lines in one frame in progressive scan mode. In QSVGA mode, each LSB represents one scan line in one field in interlaced mode and two scan lines in one frame for progressive scan mode. * Range: [02] to [98] and VSTRT[7:0] should be less than VEND[7:0] (see "VEND" on page 23) Vertical Line End Bit[7:0]: Selects the ending row of the vertical window. In full resolution mode, each LSB represents two scan lines in one field in interlaced scan mode and four scan lines in one frame in progressive scan mode. In QSVGA mode, each LSB represents one scan line in one field in interlaced mode and two scan lines in one frame for progressive scan mode. * Range: [03] to [98] and VEND[7:0] should be larger than VSTRT[7:0] (see "VSTRT" on page 23) Pixel Shift Bit[7:0]: Provides a way to fine tune the output timing of the pixel data relative to that of HREF. It physically shifts the video data output time late in unit of pixel clock. This function is different from changing the size of the window as defined by HREFST[7:0] (see "HREFST" on page 23) and HREFEND[7:0] (see "HREFEND" on page 23). It just delays the pixel output relative to HREF and does not change the window size. The highest number is [FF] and the maximum shift number is a delay of 256 pixels. (Read only = 0x7F) (Read only = 0xA2)
17
HREFST
38
RW
18
HREFEND
EA
RW
19
VSTRT
03
RW
1A
VEND
92
RW
1B
PSHFT
00
RW
1C 1D 1E-1F
MIDH MIDL RSVD
7F A2 XX
R R -
Manufacturer ID Byte - High Manufacturer ID Byte - Low Reserved
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Proprietary to OmniVision Technologies
23
OV8610
Table 13
Address (Hex)
Color CMOS SVGA (800 x 600) CAMERACHIPTM Device Control Register List
Register Name Default (Hex) R/W Description
Omni
ision
Common Control E Bit[7]: Reserved Bit[6]: Enables field/frame luminance average value calculations. Values are stored in AVG[7:0] (see "AVG" on page 33) Bit[5]: PCLK output option 0: Disables PCLK output during Sleep mode 1: Enables PCLK output during Sleep mode Aperture correction 0: Disable 1: Enable (correction strength and threshold value will be decided by COMF[7:6] for threshold and COMF[5:4] for strength (see "COMF" on page 27) AWB smart mode enable 0: Count all pixels to get AWB result. Valid only when COMB[0] = 1 (see "COMB" on page 21) and COMA[2] = 1 (see "COMA" on page 20) 1: Do not count pixels whose luminance and level are not in the range defined in AWBC[7:6] and AWBC[5:4] (see "AWBC" on page 31)
Bit[4]:
Bit[3]:
20
COME
00
RW Bit[2]:
Aperture correction mode selection 0: Correction always in whole range luminance 1: Correction only when luminance average level is larger than present level AWB fast/slow mode selection 0: AWB is in slow mode where BLUE[7:0] and RED[1:0] changes every 16/64 field decided by COMK[1] (see "COMK" on page 31). When AWB is enabled (COMA[2] = 1, see "COMA" on page 20), AWB works in fast mode until it becomes stable, then it works in slow mode. 1: AWB is always in fast mode where BLUE[7:0] and RED[7:0] is changed every field
Bit[1]:
Bit[0]:
Digital output driver capability increase selection 0: Low output driver current status 1: Double digit output driver current
21
YOFF
80
RW
Y Channel Offset Adjustment Bit[7]: Offset adjustment direction 0: Add YOFF[6:0] 1: Subtract YOFF[6:0] Bit[6:0]: Y channel digital output offset adjustment If COMG[2] = 0 (see "COMG" on page 27), this register will updated by internal circuit. Writing a value to this register through the SCCB interface will have no affect. If COMG[2] = 1, Y channel offset adjustment will use the stored value which can be changed through the SCCB interface. This register has no affect on ADC output data if COMF[1] = 0 (see "COMF" on page 27). If output is RGB raw data, this register will adjust G channel data. * Range: -127 to 127
24
Proprietary to OmniVision Technologies
Version 2.3, April 8, 2003
Omni
ision
Register Set
Table 13
Address (Hex)
Device Control Register List
Register Name Default (Hex) R/W Description U Channel Offset Adjustment Bit[7]: Offset adjustment direction 0: Add UOFF[6:0] 1: Subtract UOFF[6:0] Bit[6:0]: U channel digital output offset adjustment If COMG[2] = 0 (see "COMG" on page 27), this register will updated by internal circuit. Writing a value to this register through the SCCB interface will have no affect. If COMG[2] = 1, U channel offset adjustment will use the stored value which can be changed through the SCCB interface. This register has no affect on ADC output data if COMF[1] = 1 (see "COMF" on page 27). If output is RGB raw data, this register will adjust B channel data. * Range: -128 to 128 Oscillator Circuit Control Bit[7:6]: Select different crystal circuit power level * [11] minimum Bit[5]: ADC current control 0: Full current 1: Half current Bit[4]: Output data polarity selection 0: Positive 1: Negative Bit[3]: Horizontal array skip mode 0: Full pixel readout 1: Only read out half of horizontal pixels (400) and frame rate will double Bit[2]: Vertical array first stage skip mode 1: Only read out half of vertical lines (200) and frame rate will double System clock output selection 0: System clock. Only effective when FODD is set to output system clock 1: Half frequency of system clock Aperture correction mode selection 0: Disable aperture correction mode 1: Enable threshold relative to current gain faction
22
UOFF
80
RW
23
CLKC
04
RW
Bit[1]:
Bit[0]:
Version 2.3, April 8, 2003
Proprietary to OmniVision Technologies
25
OV8610
Table 13
Address (Hex)
Color CMOS SVGA (800 x 600) CAMERACHIPTM Device Control Register List
Register Name Default (Hex) R/W Description
Omni
ision
24
AEW
33
RW
Automatic Exposure Control (AEC) - Bright Pixel Ratio Adjustment Bit[7:0]: Used to calculate bright pixel ratio. The OV8610 AEC algorithm is a count of the whole field/frame bright pixel ratio (pixels whose luminance level is higher than a fixed level) and black pixel ratio (pixels whose luminance level is lower than a fixed level). When the bright/black pixel ratio in the range of the ratio defined by the registers AEW[7:0] and AEB[7:0] (see "AEB" on page 26), the image is stable. This register is used to define bright pixel ratio, default is 25%. Each LSB represents step: 1.3% for interlaced and 0.7% for progressive scan. Change range is [01] to [65]. Increasing AEW[7:0] will increase the bright pixel ratio. For same light condition, the image brightness will increase if AEW[7:0] increases. Note: AEW[7:0] must combine with register AEB[7:0]. The relationship must be as follows: AEW[7:0] + AEB[7:0] > [65] Automatic Exposure Control (AEC) - Black Pixel Ratio Adjustment Bit[7:0]: Used to calculate black pixel ratio. The OV7630/OV7130 algorithm is a count of the whole field/frame bright pixel ratio (pixels whose luminance level is higher than a fixed level) and black pixel ratio (pixels whose luminance level is lower than a fixed level). When the bright/black pixel ratio in the range of the ratio defined by the registers AEW[7:0] (see "AEW" on page 26) and AEB[7:0], the image is stable. This register is used to define black pixel ratio, default is 75%. Each LSB represents step: 1.3% for interlaced and 0.7% for progressive scan. Change range is [01] to [65]. Increasing AEB[7:0] will increase the black pixel ratio. For same light condition, the image brightness will decrease if AEB[7:0] increases. Note: AEW[7:0] must combine with register AEB[7:0]. The relationship must be as follows: AEW[7:0] + AEB[7:0] > [65]
25
AEB
97
RW
26
Proprietary to OmniVision Technologies
Version 2.3, April 8, 2003
Omni
ision
Register Set
Table 13
Address (Hex)
Device Control Register List
Register Name Default (Hex) R/W Description Common Control F Bit[7:6]: Aperture correction threshold selection * Range: 1% to 6.4% of the difference of neighbor pixel luminance Bit[5:4]: Aperture correction strength selection * Range: 0% to 200% of the difference of neighbor pixel luminance Reserved Digital data MSB/LSB swap 0: Normal 1: LSB to bit[7] and MSB to bit[0] Digital offset adjustment enable 0: Disable 1: Enable Black level output selection 0: No black level output 1: Output first 4/8 lines black level before valid data output for interlaced/progressive scan mode, respectively. HREF number will increase 4/8 lines relatively
Bit[3]: Bit[2]: 26 COMF B0 RW Bit[1]:
Bit[0]:
Common Control G Bit[7:6]: Reserved Bit[5]: Select smart AWB algorithm control condition 0: If strong color component is more than 40%, stop AWB 1: If strong color component is more than 60%, stop AWB Bit[4]: Bit[3]: Bit[2]: 27 COMG A0 RW Reserved Enable ADC black level calibration offset defined by registers Digital data offset adjustment manual mode enable 0: Digital data will be added/subtracted by a value defined in registers YOFF (see "YOFF" on page 24), UOFF (see "UOFF" on page 25), and VCOFF (see "VCOFF" on page 29) which are updated by internal circuit. 1: Digital data will be added/subtracted by a value defined in registers YOFF (see "YOFF" on page 24), UOFF (see "UOFF" on page 25), and VCOFF (see "VCOFF" on page 29) of which the contents can be programmed through the SCCB interface.
Bit[1]:
Digital output full range selection 0: Output range is [10] to [F0] 1: Output range is [01] to [FE] Reserved
Bit[0]:
Version 2.3, April 8, 2003
Proprietary to OmniVision Technologies
27
OV8610
Table 13
Address (Hex)
Color CMOS SVGA (800 x 600) CAMERACHIPTM Device Control Register List
Register Name Default (Hex) R/W Description
Omni
ision
Common Control H Bit[7]: RGB raw data output select 0: Normal two-line RGB raw data output format 1: One-line RGB raw data output format Bit[6]: Bit[5]: Reserved Scan mode selection 0: Interlaced mode 1: Progressive mode Freeze AEC/AGC value (effective only when COMB[0] = 1 (see "COMB" on page 21) 0: AEC/AGC normal working status 1: Registers GAIN[7:0] (see "GAIN" on page 19) and AEC[7:0] (see "AEC" on page 20) will not be updated and will hold latest value AGC disable 0: When COMB[0] = 1 (see "COMB" on page 21) and COMA[5] = 1 (see "COMA" on page 20), GAIN[7:0] (see "GAIN" on page 19) will be updated by the internal algorithm. 1: When COMB[0] = 1 and COMA[5] = 1, internal circuit will not update register GAIN[7:0]. Register GAIN[7:0] will keep latest updated value. RGB raw data output YG format 0: Y channel G R G R 1: UV channel B G B G Gain control bit 0: No change to channel gain 1: Channel gain increases 3 dB Change AGCEN input pin to FSIN input when this register is "1"
Bit[4]:
28
COMH
01
RW
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:
29
COMI
00
RW
Common Control I Bit[7]: AEC disable 0: If COMB[0] = 1 (see "COMB" on page 21), AEC[7:0] value (see "AEC" on page 20) will be updated by internal circuit 1: If COMB[0] = 1, AEC stops and register AEC[7:0] value will be held at last AEC value and NOT be updated by internal circuit Bit[6]: Slave mode selection 0: Master mode 1: Slave mode, use external SYNC and VSYNC Bit[5]: Bit[4]: Bit[3]: ADC data latch 10 ns delay option Reserved Image area used to calculate AEC/AGC 0: Whole image 1: Central 1/4 image area Reserved Version flag. For version A, value is [00]. These two bits are Read-only.
Bit[2]: Bit[1:0]:
28
Proprietary to OmniVision Technologies
Version 2.3, April 8, 2003
Omni
ision
Register Set
Table 13
Address (Hex)
Device Control Register List
Register Name Default (Hex) R/W Description Frame Rate Adjust High Bit[7]: Frame rate adjustment enable 0: Disable 1: Enable Bit[6:5]: Highest 2 bits of frame rate adjust control byte Bit[4]: Output range selection 0: [00] to [FF] 1: [01] to [FE] Bit[3]: Y brightness manual adjustment. Effective only if COMF[1] = 1 (see "COMF" on page 27) Bit[2]: Bit[1]: Enable HSYNC latched by PCLK Data output 1: One frame data output. Only when in Frame Exposure mode Fast AGC mode 0: 1: Smooth but slow AGC mode Speed double
2A
FRARH
84
RW
Bit[0]:
2B
FRARL
5E
RW
Frame Rate Adjust Low Bit[7:0]: Frame rate adjust control byte. Frame rate adjustment resolution is 0.12%. Control byte is 10 bits. Every LSB equals a decrease frame rate of 0.12%. * Range: 0.12% to 112% Reserved Common Control J Bit[7:5]: Reserved Bit[4]: Enable auto black expanding mode Bit[3]: Reserved Bit[2]: Band filter enable - this bit enables a different exposure algorithm to cut light band induced by fluorescent light Bit[1]: Reverse output frame division 1: Change drop frame to output frame Bit[0]: Reserved
2C
RSVD
XX
-
2D
COMJ
80
RW
V Channel Offset Adjustment Bit[7]: Offset adjustment direction 0: Add VCOFF[6:0] 1: Subtract VCOFF[6:0] Bit[6:0]: 2E VCOFF 80 RW V channel digital output offset adjustment If COMG[2] = 0 (see "COMG" on page 27), this register will be updated by internal circuit. Writing to this register through the SCCB interface has no effect. If COMG[2] = 1, V channel offset adjustment will use the stored value which can be changed through the SCCB interface. If COMF[1] (see "COMF" on page 27), this register has no effect on the digital output data. If output is RGB raw data, this register will adjust R/G/B data. * Range: -128 to +128
2F
REF1
19
RW
Internal Voltage Reference Control Proprietary to OmniVision Technologies 29
Version 2.3, April 8, 2003
OV8610
Table 13
Address (Hex) 30-4B 4C
Color CMOS SVGA (800 x 600) CAMERACHIPTM Device Control Register List
Register Name RSVD MEDC Default (Hex) XX 00 R/W - RW Reserved Medium Filter Option Control Bit[7]: Bit[6:0]: Description
Omni
ision
AWB step and range x 1.5 when this register is "1" Reserved
ADC Converter Option Control Bit[7:4]: Bit[3:2]: 4D ADDC 10 RW Reserved UV delay selection 00: No delay 01: No delay 10: 2tp delay 11: 4tp delay Reserved
Bit[1:0]: 4E-5F RSVD XX - Reserved
Signal Process Control A Bit[7]: Bit[6]: Bit[5]: Bit[4]: Bit[3:2]: 60 SPCA 20 RW Channel 1.5x preamplifier gain enable (3 dB) Analog half current selection Gev/God switch instead of average for G in RGB and UV channel Gev/God switch instead of average for Y channel in YUV mode Red channel preamplifier gain selection 00: 1x 01: 1.2x 10: 1.4x 11: 1.6x Blue channel preamplifier gain selection 00: 1x 01: 1.2x 10: 1.4x 11: 1.6x
Bit[1:0]:
Signal Process Control B Bit[7]: Bit[6:5]: Bit[4]: Bit[3]: Bit[2]: Bit[1:0]: AGC/AEC feedback loop using Y channel. RGB output must set it to "0" Reserved Anti-aliasing 2x option Enable RGB brightness control Brightness control BRT[7:0] (see "BRT" on page 19) range and step half Auto brightness reference level 00: 0 IRE 01: 6 IRE 10: 10 IRE 11: 20 IRE
61
SPCB
80
RW
62-64
RSVD
XX
-
Reserved
30
Proprietary to OmniVision Technologies
Version 2.3, April 8, 2003
Omni
ision
Register Set
Table 13
Address (Hex)
Device Control Register List
Register Name Default (Hex) R/W Signal Process Control C Description
65
SPCC
02
RW
Bit[7:3]: Bit[2]: Bit[1:0]:
Reserved for internal use ADC mode selection - increases range by 1.5x ADC reference selection (use recommended value only)
AWB Process Control Bit[7:6]: Select highest luminance level to be available in AWB control. This bit is only in effect if COME[3] = 1 (see "COME" on page 24) Select lowest luminance level to be available in AWB control. This bit is only in effect if COMM[3] = 1 (see "COME" on page 24) Select U level to be available in AWB control. This bit is only in effect if COMM[7] = 1 (see "COMM" on page 32) Select V level to be available in AWB control. This bit is only in effect if COMM[7] = 1 (see "COMM" on page 32)
Bit[5:4]: 66 AWBC 55 RW Bit[3:2]: Bit[1:0]:
YUV Matrix Control Bit[7:6]: UV coefficient selection, u = B - Y, v = R - Y 00: U = u, V = v 01: U = 0.938u, V = 0.838v 10: U = 0.563u, V = 0.613v 11: U = 0.5u, V = 0.877v Reserved UV signal with 3 points average Y delay selection * Range: 0tp to 3tp Reserved
67
YMXB
55
RW Bit[5]: Bit[4]: Bit[3:2]: Bit[1:0]:
AEC/AGC Reference Level Bit[7:5]: 68 ARL AC RW Bit[4:0]: 69-6F RSVD XX - Reserved Common Control K Bit[7]: Bit[6]: Bit[5]: Bit[4]: 70 COMK 80 RW Bit[3]: Bit[2]: Bit[1]: Bit[0]: HREF edge latched by PCLK falling edge Output port drive current 2x larger option Aperture correction option ZV port vertical timing selection 0: Normal TV vertical sync signal 1: VSYNC output ZV port vertical sync signal Reserved Double aperture correction strength 4x stable time less when in AWB slow mode Disable output pin internal 100K pull-down resistor Voltage reference selection (higher voltage equals brighter final stable image) * Range: [000] for lowest reference level to [111] for highest reference level Reserved
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31
OV8610
Table 13
Address (Hex)
Color CMOS SVGA (800 x 600) CAMERACHIPTM Device Control Register List
Register Name Default (Hex) R/W Common Control J Bit[7]: Description
Omni
ision
71
COMJ
00
RW
Bit[6]: Bit[5]: Bit[4]: Bit[3:2]: Bit[1:0]:
Auto brightness update rate selection 0: Fast 1: Slow PCLK output gated by HREF Change HREF output port to CHSYNC Change CHSYNC output port to HREF Highest 2-bit for HSYNC rising edge shift control (see "HSDY" on page 32) Highest 2-bit for HSYNC falling edge shift control (see "HEDY" on page 32)
Horizontal SYNC Rising Edge Shift 72 HSDY 14 RW COMJ[3:2] (see "COMJ" on page 32) and HSDY[7:0] for HSYNC rising edge shift control * Range: [000] to [3FF] step 1 pixel Horizontal SYNC Falling Edge Shift 73 HEDY 54 RW COMJ[1:0] (see "COMJ" on page 32) and HEDY[7:0] for HSYNC falling edge shift control * Range: [000] to [3FF] Common Control M Bit[7]: Bit[6:5]: 74 COMM 20 RW Enable UV smart AWB threshold controlled by COMG[5] (see "COMG" on page 27) AGC maximum gain boost control 00: 6 dB 01: 12 dB 10: 6 dB 11: 18 dB Reserved
Bit[4:0]:
Common Control N Bit[7]: AWB control mode selection 0: Always do AWB 1: Stop AWB when field/frame average level is less than threshold Reserved for internal test mode Drop one field/frame when exposure line change is bigger than a fixed number Enable exposure to go down to less than 1/120" or 1/60" in smooth AEC mode Reserved
75
COMN
0E
RW
Bit[6:4]: Bit[3]: Bit[2]: Bit[1:0]:
32
Proprietary to OmniVision Technologies
Version 2.3, April 8, 2003
Omni
ision
Register Set
Table 13
Address (Hex)
Device Control Register List
Register Name Default (Hex) R/W Common Control K Bit[7]: Bit[6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: Reserved Y/G ADC Offset Output main clock at FODD pin (see "FODD/SRAM" on page 9) Reserved Software power down mode ITU-656 timing Reserved Tri-state all timing output except data line SCCB writing bit synchronized by VSYNC Reserved Description
76
COMO
00
RW
77 78
RSVD YBAS
XX 80
- RW
Bit[7:0]:
Fixed offset to final Y/G data * Range: -128 to 128
U/B ADC Offset 79 UBAS 80 RW Bit[7:0]: Fixed offset to final U/B data * Range: -128 to 128
V/R ADC Offset 7A 7B 7C VBAS REF2 AVG 80 D8 00 RW RW RW Bit[7:0]: Fixed offset to final V/R data * Range: -128 to 128
Internal Reference Control Field/Frame average level storage. Only effective if COME[6] = 1 (see "COME" on page 24) Common Control P Bit[7]: Bit[6]: 10-bit output in one port output, less 2-bit come from UV1 and UV0 10-bit output in one port output, less 2-bit come from FODD and HREF Reserved Flip vertical safe read out. Only in YUV mode. ADC BLC level option 0: 10-bit ADC BLC level "40" (H) 1: 10-bit ADC BLC level "10" (H) Reserved
7D
COMP
08
RW
Bit[5]: Bit[4]: Bit[3]:
Bit[2:0]: 7E-81 82 83 RSVD VB VW XX 23 0B - RW RW Reserved
AEC/AGC Fast Mode Low Threshold Control (same as AEB[7:0] (see "AEB" on page 26) AEC/AGC Fast Mode High Threshold Control (same as AEW[7:0] (see "AEW" on page 26)
Version 2.3, April 8, 2003
Proprietary to OmniVision Technologies
33
OV8610
Table 13
Address (Hex)
Color CMOS SVGA (800 x 600) CAMERACHIPTM Device Control Register List
Register Name Default (Hex) R/W Common Control S Description
Omni
ision
84
COMS
00
RW
Bit[7]: Bit[6]: Bit[5:3]: Bit[2]: Bit[1:0]: Reserved
Reserved Average AGC/AEC algorithm Reserved One-line ADC option Reserved
85-88
RSVD
XX
-
Common Control V Bit[7]: Auto frame rate adjustment selection 0: One time every 1 field/frame 1: One time every 2 fields/frames Double output pixel clock Output true black line CIF one-line clock phase selection Enable ZV timing HSYNC option Bypass RGB matrix Change highest bit AGC to clock down 2 Reserved
89
COMV
00
RW
Bit[6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]:
8A 8B
RAVE BAVE
00 00
RW RW
R Channel Average Value B Channel Average Value
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.
34
Proprietary to OmniVision Technologies
Version 2.3, April 8, 2003
Omni
ision
Package Specifications
Package Specifications
The OV8610 uses a 48-pin ceramic package. Refer to Figure 10 for package information and Figure 11 for the array center on the chip.
Figure 10 OV8610 Package Specifications
.560 SQ + .012 / - .005 .430 SQ .005 .032 MIN 43 43 42 42 .350 SQ .005 31 31 30 30 .022 .004 .001 to .005 TYP .088 .011 .065 .007 .030 .002 .015 .002 .020 .002
.440 .005 .040 .003 31 42
.06 + .010 / - .005 .040 TYP 43
30
48 1
48 1 Pin 1 Index 6
.488 .004
48 1
.012 TYP REF 19 18 18 R .0075 (4 CORNERS) 19 19 .020 TYP 18 R .0075 (48 PLCS) 7 6
6 7
7
.085 TYP
Table 14
OV8610 Package Dimensions
Dimensions Millimeters (mm) 14.22 + 0.30 / -0.13 SQ 2.23 + 0.28 0.51 + 0.05 8.89 + 0.13 SQ 1.14 + 0.13 0.51 x 2.16 0.51 x 1.02 1.02 + 0.08 1.524 + 0.25 / -0.13 11.18 + 0.13 12.40 + 0.10 SQ / 13.00 + 0.10 SQ 0.55 + 0.05 Inches (in.) .560 + .012 / - .005 SQ .088 + .011 .020 + .002 .350 + .005 SQ .045 + .005 .020 x .085 .020 x .040 .040 + .003 .06 + .010 / - .005 .440 + .005 .488 + .004 SQ / .512 + .004 SQ .022 + .002
Package Size Package Height Substrate Height Cavity Size Castellation Height Pin #1 Pad Size Pad Size Pad Pitch Package Edge to First Lead Center End-to-End Pad Center-Center Glass Size Glass Height
Version 2.3, April 8, 2003
Proprietary to OmniVision Technologies
35
OV8610
Color CMOS SVGA (800 x 600) CAMERACHIPTM
Omni
ision
Sensor Array Center
Figure 11 OV8610 Sensor Array Center
Pin 1
Package
1
Die Sensor Array
Array Center (12.6 mil, 1.1 mil) (319 m, 29 m)
Package Center (0, 0)
Positional Tolerance s Die shift (x,y) = 0.15 mm (6 mils) max. Die tilt = 1 degrees max. Die rotation = 3 degrees max.
Important:
Most optical systems invert and mirror the image so the chip is usually mounted on the board with pin 1 (SVDD) down.
NOTE: Picture is for reference only, not to scale.
36
Proprietary to OmniVision Technologies
Version 2.3, April 8, 2003
Omni
ision
Package Specifications
Note:
* All information shown herein is current as of the revision and publication date. Please refer to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all documentation. OmniVision Technologies, Inc. reserves the right to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders). Reproduction of information in OmniVision product documentation and specifications is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible or liable for any information reproduced. This document is provided with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision Technologies Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this document. No license, expressed or implied, by estoppels or otherwise, to any intellectual property rights is granted herein. `OmniVision', `CameraChip' are trademarks of OmniVision Technologies, Inc. All other trade, product or service names referenced in this release may be trademarks or registered trademarks of their respective holders. Third-party brands, names, and trademarks are the property of their respective owners.
*
*
*
*
For further information, please feel free to contact OmniVision at info@ovt.com.
OmniVision Technologies, Inc. Sunnyvale, CA USA (408) 733-3030
Version 2.3, April 8, 2003
Proprietary to OmniVision Technologies
37
OV8610
Color CMOS SVGA (800 x 600) CAMERACHIPTM
Omni
ision
38
Proprietary to OmniVision Technologies
Version 2.3, April 8, 2003

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